Project

EvE Processing Element Implementation

Posted
By Danial Zuberi
1 min read

Created a Processing Element and interconnect for a genetic algorithm hardware accelerator utilizing verilog (based off the GeneSys paper), ran synthesis for area/power/timing and used testbench to debug/verify.

This was my final project in Hardware Acceleration for Machine Learning. There is an associated project report.

Hardware Verilog Synthesis Machine Learning Acceleration